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Update PCB design

Browse Source 
-> Add pad
-> Update netclass
-> Change to Two sided design
This commit is contained in:
fromost
2026-03-23 23:12:32 +08:00
parent 7a2ad7099f
commit 232fd772cb
9 changed files with 18131 additions and 16264 deletions
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1
.gitignore vendored
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@@ -3,6 +3,7 @@
/SmartWatch-backups/ /SmartWatch-backups/
**/*.lck **/*.lck
**/*.rpt **/*.rpt
/production

5226
OPL_Kicad_Library/XIAO_Series_Footprints/XIAO-ESP32-S3-SMD_PAD.kicad_mod
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File diff suppressed because it is too large Load Diff

627
OPL_Kicad_Library/custom.bak Normal file
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627
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25032
SmartWatch.kicad_pcb
View File

File diff suppressed because it is too large Load Diff

24
SmartWatch.kicad_prl
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9 9
], ],
"col_widths": [ "col_widths": [
0, 71,
0, 76,
0, 102,
0, 84,
0, 90,
0, 107,
0, 92,
0, 88,
0, 47,
0 1733
], ],
"custom_group_rules": [], "custom_group_rules": [],
"expanded_rows": [], "expanded_rows": [],

130
SmartWatch.kicad_pro
View File

@@ -53,7 +53,13 @@
"min_clearance": 0.5 "min_clearance": 0.5
} }
}, },
"diff_pair_dimensions": [], "diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [], "drc_exclusions": [],
"meta": { "meta": {
"version": 2 "version": 2
@@ -126,21 +132,21 @@
"max_error": 0.005, "max_error": 0.005,
"min_clearance": 0.15, "min_clearance": 0.15,
"min_connection": 0.0, "min_connection": 0.0,
"min_copper_edge_clearance": 0.5, "min_copper_edge_clearance": 0.3,
"min_groove_width": 0.0, "min_groove_width": 0.0,
"min_hole_clearance": 0.25, "min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25, "min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2, "min_microvia_diameter": 0.6,
"min_microvia_drill": 0.1, "min_microvia_drill": 0.3,
"min_resolved_spokes": 2, "min_resolved_spokes": 2,
"min_silk_clearance": 0.15, "min_silk_clearance": 0.15,
"min_text_height": 0.8, "min_text_height": 1.0,
"min_text_thickness": 0.08, "min_text_thickness": 0.15,
"min_through_hole_diameter": 0.3, "min_through_hole_diameter": 0.3,
"min_track_width": 0.127, "min_track_width": 0.15,
"min_via_annular_width": 0.1, "min_via_annular_width": 0.13,
"min_via_diameter": 0.6, "min_via_diameter": 0.6,
"solder_mask_to_copper_clearance": 0.0, "solder_mask_to_copper_clearance": 0.005,
"use_height_for_length_calcs": true "use_height_for_length_calcs": true
}, },
"teardrop_options": [ "teardrop_options": [
@@ -187,7 +193,9 @@
"td_width_to_size_filter_ratio": 0.9 "td_width_to_size_filter_ratio": 0.9
} }
], ],
"track_widths": [], "track_widths": [
0.0
],
"tuning_pattern_settings": { "tuning_pattern_settings": {
"diff_pair_defaults": { "diff_pair_defaults": {
"corner_radius_percentage": 80, "corner_radius_percentage": 80,
@@ -214,7 +222,12 @@
"spacing": 0.6 "spacing": 0.6
} }
}, },
"via_dimensions": [], "via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false "zones_allow_external_fillets": false
}, },
"ipc2581": { "ipc2581": {
@@ -486,16 +499,76 @@
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.6,
"name": "Default", "name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647, "priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2, "track_width": 0.15,
"tuning_profile": "", "tuning_profile": "",
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 6 "wire_width": 6
},
{
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_width": 0.2,
"microvia_diameter": 0.3,
"microvia_drill": 0.6,
"name": "GND",
"pcb_color": "rgb(0, 0, 0)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"tuning_profile": "",
"via_diameter": 0.8,
"via_drill": 0.4
},
{
"clearance": 0.25,
"diff_pair_gap": 0.25,
"diff_pair_width": 0.2,
"microvia_diameter": 0.3,
"microvia_drill": 0.6,
"name": "High Current",
"pcb_color": "rgb(255, 244, 0)",
"priority": 2,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.6,
"tuning_profile": "",
"via_diameter": 1.0,
"via_drill": 0.5
},
{
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_width": 0.2,
"microvia_diameter": 0.3,
"microvia_drill": 0.6,
"name": "Power",
"pcb_color": "rgb(255, 0, 37)",
"priority": 3,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.3,
"tuning_profile": "",
"via_diameter": 0.8,
"via_drill": 0.4
},
{
"clearance": 0.15,
"diff_pair_gap": 0.25,
"diff_pair_width": 0.2,
"microvia_diameter": 0.3,
"microvia_drill": 0.6,
"name": "Sensitive",
"pcb_color": "rgb(208, 59, 255)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.15,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3
} }
], ],
"meta": { "meta": {
@@ -503,7 +576,36 @@
}, },
"net_colors": null, "net_colors": null,
"netclass_assignments": null, "netclass_assignments": null,
"netclass_patterns": [] "netclass_patterns": [
{
"netclass": "GND",
"pattern": "Earth"
},
{
"netclass": "GND",
"pattern": "*GND"
},
{
"netclass": "Power",
"pattern": "*3V3"
},
{
"netclass": "Power",
"pattern": "*1V8"
},
{
"netclass": "High Current",
"pattern": "*BT*"
},
{
"netclass": "Sensitive",
"pattern": "*SDA"
},
{
"netclass": "Sensitive",
"pattern": "*SCL"
}
]
}, },
"pcbnew": { "pcbnew": {
"last_paths": { "last_paths": {

2681
SmartWatch.kicad_sch
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File diff suppressed because it is too large Load Diff

1
fabrication-toolkit-options.json Normal file
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@@ -0,0 +1 @@
{"ARCHIVE_NAME": "", "EXTRA_LAYERS": "", "ALL_ACTIVE_LAYERS": false, "EXTEND_EDGE_CUT": false, "ALTERNATIVE_EDGE_CUT": false, "AUTO TRANSLATE": true, "AUTO FILL": true, "EXCLUDE DNP": false, "OPEN BROWSER": true, "NO_BACKUP_OPT": false}